1. Field of the Invention
The present invention relates to a semiconductor device, more particularly, to a technique of determining power supply wirings in a semiconductor integrated circuit device.
2. Description of the Related Art
In recent years, approaches to a high integration and high speed operation of a large scale integration (LSI) device have been carried out. Thus, it has been demanded to ensure a reliable operation of the device and reduce a chip size thereof. To cope with this, it is necessary to adjust a wiring width of a respective power supply line for feeding a power supply voltage to each logic circuit block, in accordance with a respective operational frequency of the logic circuit blocks.
As an example of a conventional semiconductor device having such a power supply line, a semiconductor device of multilayer wiring structure is known which includes a first wiring layer where basic power supply lines each having a predetermined wiring width are provided for each logic circuit block, and a second wiring layer where compensating basic power supply lines are provided with a predetermined space therebetween. Note, the power supply line for feeding a power supply voltage to the respective logic circuit block is composed of the basic power supply line or lines in the first wiring layer and the compensating basic power supply line or lines in the second wiring layer which passes above the logic circuit block concerned. In the conventional layout of the power supply wirings, a wiring width of the power supply line for the respective logic circuit block has been determined irrespective of a respective operational frequency dependent on an input signal of each logic circuit block.
The conventional determination of power supply wirings does not take into consideration the operational frequencies of each logic circuit block, and thus, poses problems below. Namely, since the compensating basic power supply lines in the second wiring layer are provided with a constant space therebetween, they provide too many or excessive wirings for a logic circuit block having a relatively low operational frequency. Thus, a problem occurs in that the second wiring layer is wastefully used resulting in an increase in the chip size. On the other hand, as to a logic circuit block having a relatively high operational frequency, there is a possibility in that the compensating basic power supply lines in the second wiring layer come short in number. In this case, a problem arises in that it is impossible to ensure a reliable operation of the logic circuit block concerned.